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ALC202/ALC202a 2002/07/30 rev.1.28 1 realtek/avance logic, inc. two channel ac?97 audio codec ALC202 / ALC202a 1. features........................................................................ 2 2. general de scription .................................................... 2 3. block diagram............................................................. 3 4. pin assignments .......................................................... 5 5. pin description ............................................................ 6 5.1 digital i/o pins ...................................................... 6 5.2 analog i/o pins...................................................... 7 5.3 filter/reference...................................................... 7 5.4 power/ground ........................................................ 8 5.5 others..................................................................... 8 6. registers....................................................................... 9 6.1 mixer registers ...................................................... 9 6.1.1 mx00 reset.................................................. 10 6.1.2 mx02 master volume.................................. 10 6.1.3 mx04 headphone/true line output volume .. 10 6.1.4 mx06 mono_out volume ...................... 11 6.1.5 mx0a pc beep volume ............................ 11 6.1.6 mx0c phone volume............................... 11 6.1.7 mx0e mic volume..................................... 12 6.1.8 mx10 line_in volume ............................. 12 6.1.9 mx12 cd volume ....................................... 12 6.1.10 mx14 video volume .............................. 13 6.1.11 mx16 aux volume .................................. 13 6.1.12 mx18 pcm_out volume ........................ 13 6.1.13 mx1a record select ................................. 14 6.1.14 mx1c record gain.................................... 14 6.1.15 mx20 general purpose register................ 15 6.1.16 mx22 3d control ...................................... 15 6.1.17 mx26 powerdown control/status ............. 16 6.1.18 mx28 extended audio id ......................... 17 6.1.19 mx2a extended audio status and control.. 18 6.1.20 mx2c pcm dac rate.............................. 18 6.1.21 mx32 pcm adc rate .............................. 19 6.1.22 mx3a s/pdif channel status and control.. 19 6.2 vendor defined registers .................................... 20 6.2.1 mx6a miscellaneous control...................... 20 6.3 extension registers.............................................. 21 6.3.1 mx76 gpio setup ....................................... 21 6.3.2 mx78 gpio status...................................... 22 6.3.3 mx7a various controls .............................. 23 6.3.4 mx7c vendor id1 ................................. 24 6.3.5 mx7e vendor id2 ................................. 24 7. electrical char acteristics ......................................... 25 7.1 dc characteristics ............................................... 25 7.1.1 absolute maximum ratings......................... 25 7.1.2 threshold hold voltage ............................... 25 7.1.3 digital filter characteristics......................... 26 7.1.4 s/pdif output characteristics ...................... 26 7.2 ac timing characteristics................................... 26 7.2.1 cold reset .................................................... 26 7.2.2 warm reset .................................................. 26 7.2.3 ac-link clocks ........................................... 27 7.2.4 data output and input timing ..................... 27 7.2.5 signal rise and fall timing ......................... 28 7.2.6 ac-link low po wer mode timing ............. 28 7.2.7 ate test mode ............................................ 29 7.2.8 ac-link io pin capacitance and loading .. 29 7.2.9 spdif output............................................... 29 7.2.10 bit-clk and sdata-in state................. 29 8. analog performance characteristics ...................... 30 9. design suggestions.................................................... 32 9.1 clocking............................................................... 32 9.2 ac-link ............................................................... 33 9.3 reset..................................................................... 34 9.4 cd input .............................................................. 34 9.5 odd addressed register access .......................... 34 9.6 power-down mode............................................... 34 9.7 test mode ............................................................ 34 9.7.1 ate in circuit test mode............................ 34 9.7.2 vendor specific test mode.......................... 34 9.8 jack-detect function ........................................... 35 9.9 dc voltage volume control ............................... 36 9.10 power off cd function ............................... 37 10. application circuit ................................................. 38 11. mechanical dimensions .......................................... 41 12. revision history...................................................... 42 www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 2 1. features single chip audio codec with high s/n ratio (>90 db) compliant with ac?97 2.2 & whql specifications support of s/pdif out is compliant with ac?97 rev2.2 specifications meets performance requirements for audio on pc2001 systems meets microsoft pc99 & wlp 2.0 audio requirements 18-bit stereo full-duplex codec with independent and variable sampling rate 18-bit adc and 20-bit dac resolution four analog line-level stereo inputs with 5-bit volume control: line_in, cd, video, aux high quality differential cd input two analog line-level mono input: pc_beep,phone_in supports double sampling rate (96khz) of dvd audio playback two software selectable mic inputs +30db boost preamplifier for mic input stereo output with 6-bit volume control mono output with 5-bit volume control headphone output with 50mw/8 ? driving capability (ALC202) line output with 50mw/8 ? driving capability (ALC202a) headphone jack-detect function to mute line/mono/hp output, and to control s/pdif output 3d stereo enhancement multiple codec extension capability external amplifier power down (eapd) capability high performance converter technology power management and enhanced power saving features 2 gpio pins no external crystal/clock required 14.318mhz 24.576mhz pll saves crystal dc voltage volume control auxiliary power (vaux ) to support power off cd function power support: digital: 3.3v; analog: 3.3v/5v standard 48-pin lqfp package 2. general description the ALC202/ALC202a is an 18-bit, full duplex ac'97 2.2 compatible stereo audio c odec designed for pc multimedia systems, including host/soft audio and amr/cnr based designs. the ALC202 in corporates proprietary converter technology to achieve a high snr, greater than 90 db. the alc 202 ac'97 codec supports multiple codec ex tensions with independent variable sampling rates and built-in 3d effects. the ALC202 codec provides two pairs of stereo outputs with independent volume controls, a mono output, and multiple stereo and mono inputs, along with fl exible mixing, gain and mu te functions to provide a complete integrated audio solution for pc s. the digital interface circ uitry of the ALC202 codec operates from a 5v/3.3v power supply with eapd (external amplifier power down) control for use in notebook and pc applications. the ALC202 integrates a 50mw/8 ? headset audio amplifier into the codec, saving bom costs. the ALC202 also supports the spdif out function, which is compliant to ac'97 2.2, which can offer easy connection of pcs to consumer electronic products, such as ac3 decoder/speaker and mini disk devices. the ALC202 codec supports host/sof t audio from intel 810/815/820/845 chipsets as well as audio controller based via/sis/ali chipsets. bundled windows series driv ers (win95/98/me/2000/xp/nt) and sound effect utilities (supporting karaoke, 26-kind of environment s ound emulation, 10-band equalizer) provide an excellent entertainment package for pc users. finally, internal pll circuits generate required tim ing signals, eliminating the need for external clocking devices. there are two differences between the ALC202 and the ALC202a . first, the ALC202 includes outputs for headphones with an op-amp, and in the ALC202a, those outputs are for true line out put and have no op-amp. second, the line out channels on the ALC202 has no op-amp (1.0vrms), where the ALC202a includes an op-amp (1.0vrms). ALC202 ALC202a line-out channel no op-amp (1.0vrms) with op-amp (1.0vrms) pins 39 & 41 headphone output with op-amp true-line out without op-amp www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 3 3. block diagram stereo analog mono analog stereo digital * : default setting mx18 mx0a mx0c mx0e mx10 mx12 mx14 mx16 3d master volume mono volume dac pcm out pc-beep mic1 mic2 line-in phone cd-in video-in aux-in mx1a m u x mx1c record gain adc mono mix stereo mix pcm in headphone volume phone mic line cd video aux mx20.13 mx22 hp-out line-out mono-out mx20.9 mx20.8 spdif out control pcm out mx2a / mx3a spdif output src src ALC202 mx02 amp 0* 1 reset# mx06 mx04 yes no yes no reset# 0* 1 +20/30db www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 4 stereo analog mono analog stereo digital * : default setting mx18 mx0a mx0c mx0e mx10 mx12 mx14 mx16 3d master volume mono volume dac pcm out pc-beep mic1 mic2 line-in phone cd-in video-in aux-in mx1a m u x mx1c record gain adc mono mix stereo mix pcm in headphone volume phone mic line cd video aux mx20.13 mx22 hp-out line-out mono-out mx20.9 mx20.8 spdif out control pcm out mx2a / mx3a spdif output src src ALC202a mx02 amp 0* 1 reset# mx06 mx04 yes no yes no reset# 0* 1 +20/30db www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 5 4. pin assignments mono-out avdd2 hp-out-l avss2 gpio0 id0# eapd(jd) 123456789101112 36 35 34 33 32 31 30 29 28 27 26 25 spdifo/test 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 24 mic2 video-r aux-r phone line-in-r avss1 afilt2 vaux dvdd1 ALC202 line-out-r cd-r hp-out-r gpio1 line-out-l dcvol vrda vrad afilt1 vrefout vref avdd1 line-in-l mic1 cd-gnd cd-l video-l aux-l xtl-in xtl-out dvss1 sdata-out bit-clk dvss2 sdata-in dvdd2 sync reset# pc-beep nc id1# mono-out avdd2 true-line-out-l avss2 gpio0 id0# eapd(jd) 123456789101112 36 35 34 33 32 31 30 29 28 27 26 25 spdifo/test 23 22 21 20 19 18 17 16 15 14 13 37 38 39 40 41 42 43 44 45 46 47 48 24 mic2 video-r aux-r phone line-in-r avss1 afilt2 vaux dvdd1 ALC202a line-out-r cd-r gpio1 line-out-l dcvol vrda vrad afilt1 vrefout vref avdd1 line-in-l mic1 cd-gnd cd-l video-l aux-l xtl-in xtl-out dvss1 sdata-out bit-clk dvss2 sdata-in dvdd2 sync reset# pc-beep nc true-line-out-r id1# www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 6 5. pin description in order to reduce pin count, and therefore size and cost, some pins have multiple f unctions. in those cases, the functions are separated with a ?/? symbol. refer to the pin assignment diagram for a graphical representation. 5.1 digital i/o pins name type pin no description characteristic definition reset# i 11 ac'97 h/w rese t schmitt trigger input xtl-in i 2 crystal input pad crystal: 24.576m/14.318m crystal input external: 24.576m/14.318m external clock input xtl-out o 3 crystal output pad crystal: 24.576m/14.318m crystal output external: 24.576m/14.318m clock output sync i 10 sample sync ( 48khz) schmitt trigger input bit-clk io 6 bit clock output (12.288mhz) cmos input/output vt=0.35vdd sdata-out i 5 serial tdm ac97 output schmitt trigger input sdata-in o 8 serial tdm ac97 input cmos output gpio0 i/o 43 i: general purpose input pin-0. (can be software volume up) o: general purpose output pin-0. internally pulled high by a 50k resistor gpio1 i/o 44 i: general purpose input pin-1. (can be software volume down) o: general purpose output pin-1 internally pulled high by a 50k resistor id0# i 45 id strap 0 and pll control cmos input vt=0.35vdd, internally pulled high by a 50k resistor id1# i 46 id strap 1 and pll control cmos input vt=0.35vdd, internally pulled high by a 50k resistor eapd/jd o 47 external amplifier power down control / jack ?detect sense a low to high edge. cmos output / input, jd should be internally pulled high by a 50k resistor spdifo/ test o 48 s/pdif output / test output. digital output has 12 ma@75 ? driving capability total: 13 pins www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 7 5.2 analog i/o pins name type pin no description characteristic definition pc-beep i 12 pc speaker input analog input (1vrms) phone i 13 speakerphone input analog input (1vrms) aux-l i 14 aux left channel analog input (1vrms) aux-r i 15 aux right channel analog input (1vrms) video-l i 16 video audio left channel analog input (1vrms) video-r i 17 video audio right channel analog input (1vrms) cd-l i 18 cd audio left channel analog input (1vrms) cd-gnd i 19 cd audio analog gnd analog input (1vrms) cd-r i 20 cd audio right channel analog input (1vrms) mic1 i 21 first mic input analog input (1vrms) mic2 i 22 second mic input analog input (1vrms) line-l i 23 line input left channel analog input (1vrms) line-r i 24 line input right channel analog input (1vrms) line-out-l o 35 line-out left channel ALC202: analog output without op-amp (1.0vrms) ALC202a: analog output with op-amp (1.0vrms) line-out-r o 36 line-out right channel ALC202: analog output without op-amp (1.0vrms) ALC202a: analog output with op-amp (1.0vrms) hp-out-l o 39 ALC202: headphone out ? left ALC202a: true-line-out ? left ALC202: analog output with op-amp ALC202a: analog output without op-amp hp-out-r o 41 ALC202: headphone out ? left ALC202a: true-line-out ? left ALC202: analog output with op-amp ALC202a: analog output without op-amp mono-out o 37 speaker phone output analog output (1vrms) total: 18 pins 5.3 filter/reference name type pin no description characteristic definition vref - 27 reference voltage 1uf capacitor to analog ground vrefout o 28 ref. voltage out with 8ma drive analog output (2.25v ? 2.75v) afilt1 - 29 adc anti-aliasing filter capacitor 1000pf capacitor to analog ground. afilt2 - 30 adc anti-aliasing filter capacitor 1000pf capacitor to analog ground. vrad - 31 adc reference voltage capacitor 1uf capacitor to analog ground vrda - 32 dac reference voltage capacitor 1uf capacitor to analog ground dc vol i 33 dc voltage volume control analog input (agnd~avdd) vaux i 34 auxiliary power to keep cd and amplifier turned on. +5v analog stand-by power total: 8 pins www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 8 5.4 power/ground name type pin no description characteristic definition avdd1 i 25 analog vdd (5.0v or 3.3v) avdd2 i 38 analog vdd (5.0v or 3.3v) avss1 i 26 analog gnd avss2 i 42 analog gnd dvdd1 i 1 digital vdd (3.3v) dvdd2 i 9 digital vdd (3.3v) dvss1 i 4 digital gnd dvss2 i 7 digital gnd total: 8 pins 5.5 others name type pin no description characteristic definition test o 48 output dac clock and adc clock digital pin shared with spdifo nc - 40,34 no connection. total: 3 pins www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 9 6. registers 6.1 mixer registers access to registers with an odd number will return a 0. reading uni mplemented registers will also return a 0. x=reserved bit. reg. name d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 default 00h reset x se4 se3 se2 se1 se0 id9 id8 id7 id6 id5 id4 id3 id2 id1 id0 5990h 02h master volume mute x ml5 ml4 ml3 ml2 ml1 ml0 x x mr5 mr4 mr3 mr2 mr1 mr0 8000h/ 0000h 04h headphone volume mute x hpl5 hpl4 hpl3 hpl2 hpl1 hpl0 x x hpr5 hpr4 hpr3 hpr2 hpr1 hpr0 8000h/ 0000h 06h mono-out volume mute x x x x x x x x x x mm4 mm3 mm2 mm1 mm0 8000h/ 0000h 0ah pc_beep volume mute x x x x x x x x x x pb3 pb2 pb1 pb0 x 8000h 0ch phone volume mute x x x x x x x x x x ph4 ph3 ph2 ph1 ph0 8008h 0eh mic volume mute x x x x x bgo1 bgo0 x bc x mi4 mi3 mi2 mi1 mi0 8008h 10h line-in volume mute x x nl4 nl3 nl2 nl1 nl0 x x x nr4 nr3 nr2 nr1 nr0 8808h 12h cd volume mute x x cl4 cl3 cl2 cl1 cl0 x x x cr4 cr3 cr2 cr1 cr0 8808h 14h video volume mute x x vl4 vl3 vl2 vl1 vl0 x x x vr4 vr3 vr2 vr1 vr0 8808h 16h aux volume mute x x al4 al3 al2 al1 al0 x x x ar4 ar3 ar2 ar1 ar0 8808h 18h pcm out volume mute x x pl4 pl3 pl2 pl1 pl0 x x x pr4 pr3 pr2 pr1 pr0 8808h/ 0808h 1ah record select x x x x x lrs2 lrs1 lrs0 x x x x x rrs2 rrs1 rrs0 0000h 1ch record gain mute x x x lrg3 lrg2 lrg1 lrg0 x x x x rrg3 rrg2 rrg1 rrg0 8000h 20h general purpose pop x 3d x x x mix ms lbk x x x x x x x 0000h 22h 3d control x x x x x x x x x x x x x dp2 dp1 dp0 0000h 26h power down ctrl/status eapd pr6 pr5 pr4 pr3 pr2 pr1 pr0 x x x x ref anl dac adc 000fh 28h extended audio id id1 id0 x x rev1 rev0 amap x x x x x x spdi f x vra 0605h 2ah extended audio status x x x x x spcv x x x x spsa 1 spsa 0 x spdi f x vra 0000h 2ch pcm front out sample rate fsr 15 fsr1 4 fsr1 3 fsr1 2 fsr1 1 fsr1 0 fsr9 fsr8 fsr7 fsr6 fsr5 fs r4 fsr3 fsr2 fsr1 fsr0 bb80h 32h pcm input sample rate isr 15 isr 14 isr 13 isr 12 isr 11 isr 10 isr 9 isr 8 isr 7 isr 6 isr 5 isr 4 isr 3 isr 2 isr 1 isr 0 bb80h 3ah s/pdif ctl v 0 spsr 1 spsr 0 l cc6 cc5 cc4 cc3 cc2 cc1 cc0 pre copy /audi o pro 2000h 76h gpio setup 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 78h gpio status 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000h 7ch vendor id1 0 1 0 0 0 0 0 1 0 1 0 0 1 1 0 0 414ch 7eh vendor id2 0 1 0 0 0 1 1 1 0 0 0 1 v3 v2 v1 v0 4740h www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 10 6.1.1 mx00 reset default: 5990h writing any value to this register will start a register reset, and causes all of the registers to revert to their default valu es, then the written data is ignored. reading this register returns the id code of the specific part. bit type function 15 reserved 14:10 r return 10110b 9 r read as 0 (no support for 20-bit adc) 8 r read as 1 (support for 18-bit adc) 7 r read as 1 (support for 20-bit dac) 6 r read as 0 (no support for 18-bit dac) 5 r read as 0 (no support for loudness) 4 r read as 1 (headphone output support) 3 r read as 0 (no simulated stereo; for analog 3d block use) 2 r read as 0 (no bass & treble control) 1 r reserved, read as 0 0 r read as 0 (no dedicated mic pcm input) 6.1.2 mx02 master volume default: 8000h / 0000h these registers control the overall volume level of the output f unctions. each step on the left and right channels correspond t o 1.5db in increase/decrease in volume. bit type function 15 r/w mute control: 1: mute (- db) 0: normal 14 reserved 13:8 r/w master left volume: (mlv[5:0]) in 1.5 db steps 7:6 reserved 5:0 r/w master right volume: (mrv[5:0]) in 1.5 db steps for mrv/mlv: 00h 0 db attenuation 3fh 94.5 db attenuation when id=01, the default value is 0000h. 6.1.3 mx04 headphone/true line output volume default: 8000h / 0000h register 04h controls the headphone (ALC202)/true line (ALC202a) output volume. each step in bits 5:0 and 13:8 correspond to 1.5db in increase/decrease in volume, allowing 63 levels of volume, from 000000 to 111111. bit type function 15 r/w mute control: 1: mute (- db) 0: normal 14 reserved 13:8 r/w headphone/true line output left volume: (hpl[5:0]) in 1.5 db steps 7:6 reserved 5:0 r/w headphone/true line output right volume: (hpr[5:0]) in 1.5 db steps for hpr/hpl: 00h 0 db attenuation 3fh 94.5 db attenuation when id=01, the default value is 0000h. www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 11 6.1.4 mx06 mono_out volume default: 8000h / 0000h register 06h controls the mono volume output. mono output is the same data sent on all output channels. each step in bits 4:0 correspond to 1.5db in increase/decrease in volume, allowing 32 levels of volume from 00000 to 11111. bit type function 15 r/w mute control: 1: mute (- db) 0: normal 14:5 reserved 4:0 r/w mono master volume: (mmv[4:0]) in 1.5 db steps for mmv: 00h 0 db attenuation 1fh 46.5 db attenuation implement 5-bit volume control only. writing 1xxxxx will be interpreted as x11111 and respond when read with x11111 as well. when id=01, the default value is 0000h. 6.1.5 mx0a pc beep volume default: 8000h this register controls the input volume for the pc beep signal. each step in bits 4:1 correspond to a 3db increase/decrease in volume. 16 levels of volume are available, from 0000 to 1111. the purpose of this register is to allow the pc beep signals to pass through the ALC202, eliminating the need for an external s ystem speaker/buzzer. the pc beep pin is directly routed (internally hardwired) to the l ine-outl & r pins. if the pc speaker/buzzer i s eliminated, it is recommended to connect th e external speakers at all times so the post codes can be heard during reset. bit type function 15 r/w mute control: 1: mute (- db) 0: normal 14:5 reserved 4:1 r/w pc beep volume: (pbv[3:0]) in 3 db steps 0 reserved for pbv: 00h 0 db attenuation 0fh 45 db attenuation 6.1.6 mx0c phone volume default: 8008h register 0ch controls the tele phone input volume for soft ware modem applications. because software modem applications may not have a speaker, the codec can offer a speaker-out service. e ach step in bits 4:0 correspond to 1.5db in increase/decrease i n volume, allowing 32 levels of volume, from 00000 to 11111. bit type function 15 r/w mute control: 1: mute (- db) 0: normal 14:5 reserved 4:0 r/w phone volume: (pv[4:0]) in 1.5 db steps for pv: 00h +12 db gain 08h 0db gain 1fh -34.5db gain www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 12 6.1.7 mx0e mic volume default: 8008h register 0eh controls the microphone input volume. each step in bits 4:0 correspond to 1.5db in increase/decrease in volume, allowing 32 levels of volume, from 00000 to 11111. bit 6 enables/di sables a boost in volume to a magnification based on bits 9: 8. bit type function 15 r/w mute control: 1: mute (- db) 0: normal 14:10 reserved 9:8 r/w boost gain option: (bgo) 00: 20 db 01: 6 db 10: 12 db 11: 29.5 db (v=30*vmic-in) 7 reserved 6 r/w boost control: (bc) 0: disable 1: enable boost 5 reserved 4:0 r/w mic volume: (mv[4:0]) in 1.5 db steps for mv: 00h +12 db gain 08h 0db gain 1fh -34.5db gain if 29.5db boost gain is selected, input resistor can be reduced to save area of feedback resistor. 6.1.8 mx10 line_in volume default: 8808h register 10h controls the line_in input volume. each step in bits 4:0 correspond to 1.5db in increase/decrease in volume for the right channel, allowing 32 levels of volume, from 00000 to 11111. each step in bits 12:8 correspond to 1.5db in increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111. bit type function 15 r/w mute control: 1: mute (- db) 0: normal 14:13 reserved 12:8 r/w line-in left volume: (nlv[4:0]) in 1.5 db steps 7:5 reserved 4:0 r/w line-in right volume: (nrv[4:0]) in 1.5 db steps for nlv/nrv: 00h +12 db gain 08h 0db gain 1fh -34.5db gain 6.1.9 mx12 cd volume default: 8808h register 12h controls the cd input volume. each step in bits 4:0 correspond to 1.5db in increase/decrease in volume for the rig ht channel, allowing 32 levels of volume, from 00000 to 11111. each step in bits 12:8 correspond to 1.5db in increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111. bit type function 15 r/w mute control: 1: mute (- db) 0: normal 14:13 reserved 12:8 r/w cd left volume: (clv[4:0]) in 1.5 db steps 7:5 reserved 4:0 r/w cd right volume: (crv[4:0]) in 1.5 db steps for clv/crv: 00h +12 db gain 08h 0db gain 1fh -34.5db gain www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 13 6.1.10 mx14 video volume default: 8808h register 14h controls the video input volume. each step in bits 4:0 correspond to 1.5db in increase/decrease in volume for the right channel, allowing 32 levels of volume, from 00000 to 11111. each step in bits 12:8 correspond to 1.5db in increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111. bit type function 15 r/w mute control: 1: mute (- db) 0: normal 14:13 reserved 12:8 r/w video left volume: (vlv[4:0]) in 1.5 db steps 7:5 reserved 4:0 r/w video right volume: (vrv[4:0]) in 1.5 db steps for vlv/vrv: 00h +12 db gain 08h 0db gain 1fh -34.5db gain 6.1.11 mx16 aux volume default: 8808h register 16h controls the auxilia ry input volume. each step in bits 4:0 correspond to 1.5db in increase/decrease in volume for the right channel, allowing 32 levels of volume, from 00000 to 11111. each step in bits 12:8 correspond to 1.5db in increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111. bit type function 15 r/w mute control: 1: mute (- db) 0: normal 14:13 reserved 12:8 r/w aux left volume: (alv[4:0]) in 1.5 db steps 7:5 reserved 4:0 r/w aux right volume: (arv[4:0]) in 1.5 db steps for alv/arv: 00h +12 db gain 08h 0db gain 1fh -34.5db gain 6.1.12 mx18 pcm_out volume default: 8808h / 0808h register 18h controls the pcm_out output volume. each step in bits 4:0 correspond to 1.5db in increase/decrease in volume for the right channel, allowing 32 levels of volume, from 00000 to 11111. each step in bits 12:8 correspond to 1.5db in increase/decrease in volume for the left channel, allowing 32 levels of volume, from 00000 to 11111. bit type function 15 r/w mute control: 1: mute (- db) 0: normal 14:13 reserved 12:8 r/w pcm volume: (plv[4:0]) in 1.5 db steps 7:5 reserved 4:0 r/w pcm right volume: (prv[4:0]) in 1.5 db steps for plv/prv: 00h +12 db gain 08h 0db gain 1fh -34.5db gain when id=01, the default value is 0808h. www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 14 6.1.13 mx1a record select default: 0000h register 1ah controls the record input volume. each step in bits 2:0 correspond to 1.5db in increase/decrease in volume for the right channel, allowing 7 levels of volume, from 000 to 111. each step in bits 10:8 correspond to 1.5db in increase/decrease in volume for the left channel, allowing 7 levels of volume, from 000 to 111. bit type function 15:11 reserved 10:8 r/w left record source select (lrs[2:0]) 7:3 reserved 2:0 r/w right record source select (rrs[2:0]) for lrs 0 mic 0 cd left 0 video left 0 aux left 0 line left 0 stereo mixer output left 0 mono mixer output 7 phone for rrs 0 mic 0 cd right 0 video right 0 aux right 0 line right 0 stereo mixer output right 0 mono mixer output 0 phone 6.1.14 mx1c record gain default: 8000h register 1ch controls the record gain. each step in bits 3:0 correspond to 1.5db in increase/decrease in gain for the right channel, allowing 16 levels of gain, from 0000 to 1111. each step in bits 11:8 correspond to 1.5db in increase/decrease in gain for the left channel, allowing 16 levels of gain, from 0000 to 1111. bit type function 15 r/w mute control: 1: mute (- db) 0: normal 14:12 reserved 11:8 r/w left record gain select: (lrg[3:0]) in 1.5 db steps 7:4 reserved 3:0 r/w right record gain select: (rrg[3:0]) in 1.5 db steps for lrg/rrg: 0fh +22.5db 00h 0 db (no gain) www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 15 6.1.15 mx20 general purpose register default: 0000h this register is used to control several functions. bit 13 enable s or disables 3d control. bit 9 allows selection of mono outpu t. bit 8 controls the mic selector. bit 7 enables loopback of the ad output to the da input without involving the ac-link, allowing for full system performance measurements. bit type function 15:14 reserved , read as 0 13 r/w 3d control: 1: on 0: off 12:10 reserved , read as 0 9 r/w mono output select: 1: mic 0: mix 8 r/w mic select: 1: mic 2 0: mic 1 7 r/w ad to da loop-back control: 1: enable 0: disable 6:0 reserved 6.1.16 mx22 3d control default: 0000h this register is used to control the 3d stereo enhancement function built into the ac?97 component. the register bits, dp2-dp0 are used to control the separation ratios in the 3d control for both line_out and dac_out. the 3d stereo enhancement function provides for a deeper a nd wider sound experience with a potential 6-speaker arrangement. note that the 3d bit in the general purpose register (bit 13) must be set to 1 to enable this function. bit type function 15:3 reserved , read as 0 2:0 r/w depth control (dp[2:0]) 3d effect control dp[2:0] function dp[2:0] function 000 0% (off*) 100 50% 001 12.5% 101 67.5% 010 25% 110 75% 011 37.5 111 100% * default www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 16 6.1.17 mx26 powerdown control/status default: 000fh this read/write register is used to program powerdown states and monitor subsystem readiness. the lower half of this register i s read only status; a ?1? indicating that the subsection is ?ready.? ready is defined as the subsection?s ability to perform in i ts nominal state. when this register is written, the bit values that come in on ac-link will have no effect on read only bits 0-7 and bit 15. when the ac-link ?codec ready? indicator bit (sdata_in slot 0, bit 15) is a 1, it indicates that the ac-link and ac?97 control and status registers are in a fully operational state. the ac?97 controller must further probe this powerdown control /status register to determine exactly which subsections, if any are ready. bit type function 15 r/w pr7 external amplifier power down (eapd): 1: power down 0: normal 14 r/w pr6 : 1: power down headphone out (hp-out, pin-39/41) 0: normal 13 r/w pr5: 1: disable internal clock 0: normal 12 r/w pr4: 1: power down ac-link 0: normal 11 r/w pr3: 1: power down mixer (vref off) 0: normal 10 r/w pr2: 1: power down mixer (vref still on) 0: normal 9 r/w pr1: 1: power down pcm dac 0: normal 8 r/w pr0: 1: power down pcm adc and input mux 0: normal 7:4 reserved , read as 0 3 r vref status: 1: vref is up to normal level 0: not yet ready 2 r analog mixer status: 1: ready 0: not yet ready 1 r dac status: 1: ready 0: not yet ready 0 r adc status: 1: ready 0: not yet ready true table for power down mode : adc dac mixer verf aclink int clk hp-out eapd pr0=1 pd pr1=1 pd pr2=1 pd pd pr3=1 pd pd pd pd pd pr4=1 pd pd pd pr5=1 pd pd pd pr6=1 pd pr7=1 pd pd: power down blank: don?t care ? if mixer is power down (pr2=1 or pr3=1), the line-out (pin-35/36) is shut down and its output is floated. ? if headphone-out is power down (pr6=1), the hp-out (pin-39/41) is shut down and its output is floated. www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 17 6.1.18 mx28 extended audio id default: 0605h the extended audio id register is a read only register used to communicate information to the digital controller on two functio ns. id1 and id0 echo the configuration of the codec as defined by the pr ogramming of pins 45 and 46 extern ally. ?00? returned defines t he codec as the primary codec, while any other code identifies the codec as one of three secondary codec possibilities. bit type function 15 r id1 14 r id0 13:12 reserved , read as 0 11:10 r rev[1:0]=01 to indicate that the ALC202 is ac?97 rev2.2 compliant 9 r amap read as 1 (dac mapping based on id) 8:6 reserved , read as 0 5:4 r/w dac slot assignment dsa[1:0] (default value depends on id[1:0]) dsa[1:0] controls the dac slot assignment, as described in ac?97 rev2.2. 3 reserved , read as 0 2 r spdif read as 1 (s/pdif is supported) 1 r dra read as 1 0 r vra read as 1 (variable rate audio is supported) id[1:0] depend on the states of pins 46, 45, 44, and 43 when power-on reset or ac97_reset# is active. refer to section 9.1 for detailed information on configuration of id[1:0]. the ALC202 maps dac slot according to the followi ng table: (default maps to ac?97 spec. rev2.2) dsa[1:0] left dac slot # right dac slot # comment 0,0 3 4 default when id[1:0]=00 0,1 7 8 default when id[1:0]=01,10 1,0 6 9 default when id[1:0]=11 1,1 10 11 - www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 18 6.1.19 mx2a extended audio status and control default: 0000h this register contains two active bits for powerdown and status of the surrounding dacs. bits 0, 1 & 2 are read/write bits whic h are used to enable or disable vra, dra a nd spdif respectively. bits 4 & 5 are read/w rite bits used to determine the ac-link slot assignment of the s/pdif. bit 10 is a read only bit which tells the controller if the s/pdif configuration is valid. bit type function 15 r/w validity configuration of s/pdif output: (vcfg) combines with mx3a.15 to decide validity control in s/pdif output signal. 14:11 na reserved 10 r s/pdif configuration valid: (spcv) 1: current s/pdif c onfiguration {spsa,spsr,dac/slot rate} is valid 0: current s/pdif conf iguration {spsa,spsr,dac/slot rate} is not valid 9:6 reserved 5:4 r/w s/pdif slot assignment: (spsa[1:0]) 00: s/pdif source data assigned to ac-link slot3/4 01: s/pdif source data assigned to ac-link slot7/8 (default when id=00) 10: s/pdif source data assigned to ac-link slot6/9 (default when id=01,10) 11: s/pdif source data assigned to ac-link slot10/11 (default when id=11) 3 reserved 2 r/w spdif: 1: enable 0: disable (spdifo is in high impedance) 1 r/w dra: 1: enable 0: disable 0 r/w vra: 1: enable 0: disable if vra = 0, ALC202 adc/dac operate at fixed 48khz sampling rate. otherwise, it operates with variable sampling rate defined in mx2c and mx32. vra also control write operation of mx2cand mx32. dra can be written when (id=00)&(dsa=00), otherwise it is always 0. if dra = 1, dac operates at a fixed 96khz sampling rate . the pcm(n) and pcm(n+1) data is captured in the same frame. in this mode, mx2c is fixed at bb 80h, mx32 and adc is still controlled by vra. 6.1.20 mx2c pcm dac rate default: bb80h the ALC202 allows adjustment of the front center output sample rate. this register is used to adjust the sample rate. by changing the values, sampling rates from 8000 to 48000 can be chosen. bit type function 15:0 r/w output sampling rate: fosr[15:0] the ALC202 supports the following sampling rates, as required in the pc99/pc2001 design guide. sampling rate fosr[15:0] 8000 1f40h 11025 2b11h 12000 2ee0 16000 3e80h 22050 5622h 24000 5dc0 32000 7d00h 44100 ac44h 48000 bb80h note that if the value written is not s upport, the closest value is returned. when mx2a.0=0 (vra is disable), this register will return bb80h when read. www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 19 6.1.21 mx32 pcm adc rate default: bb80h the ALC202 allows adjustment of the surround output sample rate. th is register is used to adjust the sample rate. by changing the values, sampling rates from 8000 to 48000 can be chosen. bit type function 15:0 r/w output sampling rate: fisr[15:0] the ALC202 supports the following sampling rates, as required in the pc99/pc2001 design guide. sampling rate fisr[15:0] 8000 1f40h 11025 2b11h 12000 2ee0 16000 3e80h 22050 5622h 24000 5dc0 32000 7d00h 44100 ac44h 48000 bb80h note that if the value written is not s upport, the closest value is returned. when mx2a.0=0 (vra is disable), this register will return bb80h when read. 6.1.22 mx3a s/pdif channel status and control default: 2000h bit type function 15 r/w validity control: control v bit in sub-frame. 1: the v bit in sub-frame is always send as 1 to indicate the invalid data is not suitable for receiver. 0: the v bit (valid flag) in sub-frame depends on whether the s/pdif data is under-run or over-run. 14 r double rate s/pdif: (drs) the ALC202 does not support double rate s/pdif. this bit is always 0. 13:12 r/w s/pdif sample rate: spsr[1:0] 00: sample rate set to 44.1khz, fs[ 0:3 ]=0000 01: reserved 10: sample rate set to 48.0khz, fs[ 0:3 ]=0100 (default) 11: sample rate set to 32.0khz, fs[ 0:3 ]=1100 11 r/w generation level (level) 10:4 r/w category code (cc[6:0]) 3 r/w preemphasis: (pre) 1: filter preemphasis is 50/15 sec 0: none 2 r/w copyright: (copy) 1: asserted 0: not asserted 1 r/w non-audio data type: (/audio) 1: ac3 or other digital non-audio data 0: pcm data 0 r professional or consumer format: (pro) 1: professional format 0: consumer format the ALC202 supports consumer channel status format, so this bit is always 0. www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 20 the consumer channel status block (bit0~bit31): 0 1 2 3 4 5 6 7 pro=0 /audio copy pre 0 0 0 0 8 9 10 11 12 13 14 15 cc0 cc1 cc2 cc3 cc4 cc5 cc6 level 16 17 18 19 20 21 22 23 0 0 0 0 0 0 0 0 24 25 26 27 28 29 30 31 fs0 fs1 fs2 fs3 0 0 0 0 the ?v? bit in the sub-frame is determined by validity control (mx3a.15) and vcfg (mx2a.15): validity vcfg operation 0 0 if s/pdif fifo is under-run, the ?v? bit in the sub-frame is set to indicate that the s/pdif data is invalid. 0 1 if s/pdif fifo is under-run, the ?v? bit in the sub-frame is alway s 0, and pads the data with ?0?s. 1 0 the ?v? bit is always 1, and data bits (bit 8 ~ bit 27) should be forced to 0. 1 1 reserved 6.2 vendor defined registers the ALC202 supports only one vendor defined register. this regist er, not defined in the ac?97 specifications, is available to realtek and realtek customer s for specialized functions. 6.2.1 mx6a miscellaneous control default: 0000h the default source of s/pdif output is data sent by controller. when bit 12 is set, s/pdif data comes from the adc of the ALC202. to keep data concurrence, software must guarantee that the sample rates in mx32 and mx3a[13:12] are the same. spcv is no longer a validity for s/pdif confi guration. if software does not keep the sa me sample rates, the s/pdif output will be auto forbidden by hardware, a nd undefined consequences may occur. bit type function 15:14 reserved 13 r/w dac pcm(n+1) slot# select (when dra=1) 1: pcm(n+1) captured from slot-7/8 0: pcm(n+1) captured from slot-10/11. (default in ac?97 rev2.2) 12 r/w s/pdif source: 1: s/pdif data is from adc 0: s/pdif data is from controller (default) 11:4 reserved 3 r/w spdif out volume control ? mute bit: 1: clamp spdif output data to 0. (mut e) 0: normal 2:0 r/w spdif out volume control ? in 6 db step attenuation: 000: 0db 001: -6db 010: -12db ? 111: -42db www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 21 6.3 extension registers 6.3.1 mx76 gpio setup default: 0000h bit type function 15 r/w gpio status indication in sdata_in: 1: the status of gpio0/gpio1/jd and its valid tag are indicated in sdata_in 0: the status of gpio0/gpio1/jd and its valid tag are not indicated in sdata_in. 14:8 reserved 7 r/w dcvol (dc volume control) interrupt enable: 1: enable 0: disable when the 5-bot volume code in the ramp counter adc is changed (mx74.[4:0] is different from its previous value), it will trigger the dcvol interrupt in bit0 of sdata_in?s slot-12. 6 r/w jd (jack-detect) interrupt enable: (when pin-47 is used as jack-detect) 1: enabled 0: disabled a low to high transaction will trigger the jd interrupt in bit0 of sdata_in?s slot-12. 5 r/w gpio1 interrupt enable: (when gpio1 is used as input) 1: enabled 0: disabled a low to high transaction will trigger the gpio interrupt in bit0 of sdata_in?s slot-12. 4 r/w gpio0 interrupt enable: (when gpio0 is used as input) 1: enabled 0: disabled a low to high transaction will trigger the gpio interrupt in bit0 of sdata_in?s slot-12. 3:2 reserved 1 r/w gpio1primitiveness control: 1: set gpio1 as output pin 0: set gpio1 as input pin 0 r/w gpio0 primitiveness control: 1: set gpio0 as output pin 0: set gpio0 as input pin software can be designed to enable the jd in terrupt when a ?jack detection? event occurs. the bit-allocation of gpio/j d/dcvol status in ac-link: *gpint = (mx78.7 | mx78.6 | mx78.5 | mx78.4) frame addr data pcml pcmr gpio 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sync sdata-in (slot-0) sdata-in (slot-12) 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 210 gpio1 gpio0 gpint gpint jd | dcvol www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 22 6.3.2 mx78 gpio status default: 0000h bit type function 15:10 reserved 9 r/w gpio1 output control: 1: drive gpio1 high 0: drive gpio1 low 8 r/w gpio0 output control: 1: drive gpio0 as high 0: drive gpio0 as low 7 r/w dcvol interrupt status: (dcvol_is) 1: dcvol interrupt 0: no dcvol interrupt dcvol_is= (mx76.7=1)&(mx74.[4:0] is changed). write 1 to clear this status bit. 6 r/w jd interrupt status: (jd_is) 1: jd interrupt 0: no jd interrupt jd_is= (mx78.2=1)&(mx76.6=1) & (jd low-to-high transition). write 1 to clear this status bit. 5 r/w gpio1 interrupt status: (gpio1_is). (when gpio1 is used as input) 1: gpio1 interrupt 0: no gpio1 interrupt gpio1_is= (mx76.1=0)&(mx76.5=1) & (gpio1 low-to-high transition). write 1 to clear this status bit. 4 r/w gpio0 interrupt status: (gpio0_is). (when gpio0 is used as input) 1: gpio0 interrupt 0: no gpio0 interrupt gpio0_is= (mx76.0=0)&(mx76.4=1) & (gpio0 low-to-high transition) write 1 to clear this status bit. 3 na reserved 2 r jack-detect event: (jdevt) 1: jack-detect event has occurred 0: no jack-detect event has occurred jdevt = mx7a.1 1 r gpio1 input status: 1: gpio1 is driven high by external device (input) 0: gpio1 is driven low by external device (input) 0 r gpio0 input status: 1: gpio0 is driven high by external device (input) 0: gpio0 is driven low by external device (input) gpio interrupt (gpint) in bit0 of sdata_in?s slot-12 = (mx78.4 | mx78.5 | mx78.6 | mx78.7). when gpio1/0 is used as input pin, its status will be also reflected in bit2/1 of sdin?s slot-12. once gpio1/0 is used as output pin, the bit2/1 of sdata_in?s slot-12 is always 0. the gpiox is internally pulled high by a weak resistor. www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 23 6.3.3 mx7a various controls default: 57c0h this register is used for several types of information. bit type function 15 r clock source selection: (xtlsel) 1: 14.318mhz crystal is used. 14.318m 24.576m digital pll is enabled. (xtlsel is pulled low) 0: 24.576mhz crystal is used. dpll is bypassed. (xtlsel is floating or open) 14 r/w buffer under-run policy: (bup) 1: hold a zero pcm sample when fifo is under-run 0: hold the last pcm sample when fifo is under-run 13 r/w digital high-pass filter to eliminate variation in dc offset: (enhpf) 1: enabled (default) 0: disabled 12 r/w enable dc voltage volume control: 1: enable. master volume and headphone volume are determined by the sum of the 5-bit volume code and mx02/mx04/mx06. 0: disable. reset 5-bit volume code to 0. 11:8 na reserved 7 r/w pin-48 function selection: 1: test 0: s/pdif output (default) 6 r/w output value of test: (when bit-7 is set) 1: dac clk 0: adc clk 5 r/w pin-47 function selection: 1: jack-detect input 0: eapd output (default) 4 r/w hp-out control: 1: hp-out is auto muted by h/w when jds=1 0: normal 3 r/w mono-out control: 1: mono-out is auto muted by h/w when jds=1 0: normal 2 r/w spdif output gating: 1: spdif output is gated with jds 0: spdif output is not gated with jds 1 r jack-detect status: (jds) 1: jd is floating or pulled high 0: jd is pulled low this bit always indicates the jd pin status after power on. 0 r/w line-out control: 1: line-out is auto muted by h/w when jds=1 0: normal www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 24 6.3.4 mx7c vendor id1 default: 414ch the two registers (mx7c vendor id1 and mx7e vendor id2) contai n four 8-bit id codes. the first three codes have been assigned by microsoft for plug and play definitions. the fourth code is a realtek assigned code identifying the ALC202. the mx7c vendor id1 register contains the value 414ch, which is the first and second characters of the microsoft id code. the mx7c vendor id2 register contains the value 4740h, which is the third of the microsoft id code. bit type function 15:0 r vendor id ?al? 6.3.5 mx7e vendor id2 default: 4740h bit type function 15:8 r vendor id ?g? 7:4 r chip id 0100 (ALC202) 3:0 r version number: 00: version a. due to whql issues, the version number is always 0. www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 25 7. electrical characteristics 7.1 dc characteristics 7.1.1 absolute maximum ratings parameter symbol minimum typical maximum units power supplies digital analog dvdd avdd 3.0 3.0 3.3 5.0 3.6 5.5 v v operating ambient temperature ta 0 - +70 o c storage temperature ts +125 o c esd (electrostatic discharge) susceptibility voltage pin-38 over 4000v (pass 4000v) pin-2, 6, 10, 11 over 4500v (pass 4500v) others over 5000v (pass 5000v) 7.1.2 threshold hold voltage dvdd= 3.3v 5%, t ambient =25 0 c, with 50pf external load. parameter symbol minimum typical maximum units input voltage range v in -0.30 - dvdd+0.30 v low level input voltage (sync,sdata_out,reset#) v il - 0.7 0.35dvdd v low level input voltage (xtal_in,bit_clk) v il - 1.0 0.35dvdd v low level input voltage (other digital pins) v il - 1.2 0.35dvdd v high level input voltage (sync,sdata_out,reset#) v ih 0.4dvdd 1.7 - v high level input voltage (xtal_in,bit_clk) v ih 0.4dvdd 2.2 - v high level input voltage (other digital pins) v ih 0.4dvdd 1.7 - v high level output voltage v oh 0.9dvdd - v low level output voltage v ol - - 0.1dvdd v input leakage current - -10 - 10 a output leakage current (hi-z) - -10 - 10 a output buffer drive current - - 5 - ma internal pull up resistance - 50k 100k 200k ? www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 26 7.1.3 digital filter characteristics filter symbol minimum typical maximum units adc lowpass filter passband 0 - 19.2 khz stopband 28.8 khz stopband rejection -76.0 db passband frequency response +- 0.15 db dac lowpass filter passband 0 - 19.2 khz stopband 28.8 khz stopband rejection -78.5 db passband frequency response +- 0.15 db 7.1.4 s/pdif output characteristics dvdd= 3.3v, t ambient =25 0 c, with 75 ? external load. parameter symbol minimum typical maximum units high level output voltage v oh 3.0 3.3 v low level output voltage v ol - 0 0.5 v 7.2 ac timing characteristics 7.2.1 cold reset parameter symbol minimum typical maximum units reset# active low pulse width t rst_low 1.0 - - s reset# inactive to bit_clk startup delay t rst2clk 162.8 - - ns cold reset timing diagram 7.2.2 warm reset parameter symbol minimum typical maximum units sync active high pulse width t sync_high 1.0 - - s sync inactive to bit_clk startup delay t sync2clk 162.8 - - ns warm reset timing diagram www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 27 7.2.3 ac-link clocks parameter symbol minimum typical maximum units bit_clk frequency - 12.288 - mhz bit_clk period t clk_period - 81.4 - ns bit_clk output jitter - - 750 ps bit_clk high pulse width (note 2) t clk_high 36 40.7 45 ns bit_clk low pulse width (note 2) t clk_low 36 40.7 45 ns sync frequency - 48.0 - khz sync period t sync_period - 20.8 - s sync high pulse width t sync_high - 1.3 - s sync low pulse width t sync_low - 19.5 - s note 1: worse case duty cy cle restricted to 45/55. bit_clk and sync timing diagram 7.2.4 data output and input timing parameter symbol minimum typical maximum units output valid delay from rising edge of bit_clk t co - - 15 ns note 1: timing is for sdata and sync outputs with respect to bit_clk at the device driving the output. note 2: 50pf external load parameter symbol minimum typical maximum units input setup to falling edge of bit_clk t setup 10 - - ns input hold from falling edge of bit_clk t hold 10 - - ns note: timing is for sdata and sync outputs with respect to bit_clk at the device driving the output. parameter symbol minimum typical maximum units bit_clk combined rise or fall plus flight time - - 7 ns sdata combined rise or fall plus flight time - - 7 ns note: combined rise or fall plus flight times are provided for worst case scenario modeling purposes. data output and input timing diagram www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 28 7.2.5 signal rise and fall timing parameter symbol minimum typical maximum units bit_clk rise time trise clk - - 6 ns bit_clk fall time tfall clk - - 6 ns sync rise time trise sync - - 6 ns sync fall time tfall sync - - 6 ns sdata_in rise time trise din - - 6 ns sdata_in fall time tfall din - - 6 ns sdata_out rise time trise dout - - 6 ns sdata_out fall time tfall dout - - 6 ns note 1: 75pf external load (50 pf in ac?97 rev2.1) note 2: rise is from 10% to 90% of vdd (v ol to v oh ) note 3: fall is from 90% to 10% of vdd (v oh to v ol ) signal rise and fall timing diagram 7.2.6 ac-link low power mode timing parameter symbol minimum typical maximum units end of slot 2 to bit_clk, sdata_in low t s2_pdown - - 1.0 s ac-link low power mode timing diagram www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 29 7.2.7 ate test mode to meet ac?97 rev2.2 specifications, eapd, spdifo, bit_ clk and sdata_in should be floating in test mode. parameter symbol minimum typical maximum units setup to trailing edge of reset# (also applies to sync) t setup2rst 15.0 - - ns rising edge of reset# to hi-z delay t off - - 25.0 ns ate test mode timing diagram 7.2.8 ac-link io pin capacitance and loading output pin 1 codec 2 codec 3 codec 4 codec bit_clk (must support 2 codecs) 55pf 62.5pf 75pf 85pf sdata_in 47.5pf 55pf 60pf 62.5pf 7.2.9 spdif output spdif_out minimum typical maximum units rise time/fall time 0 10 % duty cycle 45 55 % t (h) t (l) t (r) t (f) 90% 50% 10% notes: rise time = 100 * t (r) / (t (l) + t (h) )% fall time = 100 * t (f) / (t (l) + t (h) )% duty cycle = 100 * t (h) / (t (l) + t (h) )% 7.2.10 bit-clk and sdata-in state when reset# is active, bit-clk and sdata-in must be floating. the ac-link signals are driven by another ac?97 on a cnr board. this requirement is not mentioned in the ac?97 specifi cations rev 2.1. please refer to cnr (communication network riser) specifications rev.1.0 pages 23~25 or ac?97 rev.2.2 for detailed information. www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 30 8. analog performance characteristics standard test conditions: t ambient =25 0 c, dvdd=3.3v 5%,avdd=5.0v 5% 1khz input sine wa ve; sampling frequency=48khz; 0db=1vrms 10k ? /50pf load; test bench characterization bw: 10hz~22khz 0db attenuation; tone and 3d disabled parameter minimum typical maximum units full scale input voltage: line inputs (mixers) line inputs (a/d) mic input (0 db) mic input (20 db boost) - - - - 1.6 1.2 1.6 0.16 - - - - vrms full scale output voltage line-out (ALC202 / ALC202a) hp-out (ALC202 / ALC202a) - - 1.1 / 1.5 1.5 / 1.1 - - vrms vrms analog to analog s/n: cd to line-out other to line-out - - 95 95 - - db analog frequency response 16 - 22,000 hz s/n (a-weighted): d/a a/d - - 90 85 - - db total harmonic distortion (a-weighted): d/a a/d - - -80 -78 - - db d/a & a/d frequency response 20 - 19,200 hz transition band 19,200 - 28,800 hz stop band 28,800 - hz stop band rejection -75 - - db out-of-band rejection - -65 - db group delay - - 1 ms power supply rejection - -65 - db mic amplifier 20db gain 18 20 22 db master volume (line- / hp-out): 64 step step size attenuation control range - 0 1.5 - - -94.5 db db master volume (mono-out): 32 step step size attenuation control range - 0 1.5 - - -46.5 db db pc beep volume 16 steps: step size attenuation control range - 0 3.0 - - -45 db db analog mixer volume 32 steps: step size gain control range - -34.5 1.5 - - +12 db db record gain 16 steps: step size gain control range - 0 1.5 - - +22.5 db db dc volume control: 32 step gain control range 0 db dc voltage mute dc voltage 0 4.7 -43 0.1 db v v input impedance (gain = 0db, mixer = off) line-in, cd-in, aux-in, video-in mic1 / mic2 pcbeep, phone 64 64 / 16 16 k ? k ? k ? cont? www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 31 output impedance line-out (ALC202 / ALC202a) hp-out (ALC202 / ALC202a) mono-out (ALC202 / ALC202a) 280 / 1 1 / 280 500 ? ? ? amplifier maximum output power @20 ? load @8 ? load 80 60 mw mw power supply current va=5.0v (powered speaker / 20 ? / 4 ? ) va=3.3v (powered speaker / 20 ? / 4 ? ) vd=3.3v - 40 / 88 / 150 40 / 88 / 150 20 ma ma power down current va=5.0v / 3.3v vd=3.3v - - 2 / 1 3 ma ma vrefout - 2.50 - v vrefout drive current 8 12 ma www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 32 9. design suggestions 9.1 clocking the clock source and id[1:0] are determined by status latched from pin-46/45/44/43 on the power-on reset and ac97_reset# trailing edge . different clock source configurations are listed below. configuration operation & id[1:0] pin-46 / 45 (id1# / id0#) pin-44 / 43 (gpio1 / 0) id[1:0] bit-clk clock source nc / nc x 00 (primary) output crystal or external 24.576mhz source input from xtal-in. low / x x 00 (primary) output external 14.318mhz clock source input from xtal-in. nc / low nc / nc 01 (secondary) input 12.288mhz clock input from bit-clk. nc / low nc / low 01 (secondary) input 12.288mhz clock input from bit-clk. nc / low low/nc 10 (secondary) input 12.288mhz clock input from bit-clk. nc / low low / low 11 (secondary) input 12.288mhz clock input from bit-clk. *low: pulled low by a 0 ? resistor. nc: not connected or pulled high x: don?t care *pin-46/45/44/43 are all internally pulled high by weak resistors. standard primary mode (id=00), use external or crystal 24.576mhz as clock source. external 14.318m is used as clock source, digital pll transmit 14.318m clock into 24.576mhz. standard secondary mode (id= 01), ALC202 receive external 12. 288mhz clock from bit-clk pin. extended secondary mode (id=01,10,11), pin-44/43 are used to configure id, al c202 receive extern al 12.288mhz clock from bit-clk pin. www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 33 9.2 ac-link when the ALC202 receives serial data from the ac97 controller, it samples sdat a_out on the falling edge of bit_clk. when the ALC202 sends serial data to the ac97 controller, it starts to drive sdata_in on the rising edge of bit_clk. the ALC202 will return any uninstalled bits or registers with 0 for read operations. th e ALC202 also stuffs the unimplemented slot or bit with 0 in sdata_in. note that ac-link is msb-justified. refer to ?audio codec ?97 component specification revision 2.1/2.2? for details. 0 1 2 3 4 5 6 7 8 9 10 11 12 tag cmd data pcm l pcmr spdif l spdif r tag add r data pcm l pcmr default ALC202 slot arrangement ? codec id = 00 0 1 2 3 4 5 6 7 8 9 10 11 12 tag cmd data spdif l pcm l pcmr spdif r tag add r data pcm l pcmr default ALC202 slot arrangement ? codec id = 01,10 0 1 2 3 4 5 6 7 8 9 10 11 12 tag cmd data pcm l pcmr spdif l spdif l tag add r data pcm l pcmr default ALC202 slot arrangement ? codec id = 11 slot# s yn c sdata-out sdata-in slot# s yn c sdata-out sdata-in slot# s yn c sdata-out sdata-in www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 34 9.3 reset there are 3 types of reset operations: cold, warm and register. reset type trigger condition codec response cold assert reset# for a specified period reset all hardware logic and all registers to its default value. register write register indexed 00h reset all registers to its default value. warm driven sync high for specified period without bit_clk reactivates ac-link, no cha nge to register values. the ac97 controller should drive sync and sdata_out low duri ng the period of reset# assertion to guarantee that the ALC202 has reset successfully. 9.4 cd input it is important to pay attention to differential cd input. below is an example of differential cd input. example of differential cd input 9.5 odd addressed register access the ALC202 will return ?0000h? when odd-addre ssed and unimplemented registers are read. 9.6 power-down mode it is important to pay special attention to the power down control register (index 26h), especially pr4 (powerdown ac-link). 9.7 test mode to provide compatibility with ac?97 rev2.2, the ALC202 will float its digital output pi ns in both ate and vendor-specific test modes. please refer to ac?97 rev2.2 section 9.2 for a detailed description of the test modes. 9.7.1 ate in circuit test mode sdata_out is sampled high at the trailing edge of reset# . in this mode, the ALC202 will drive bit_clk, sdata_in, eapd and spdifo to high impedance. 9.7.2 vendor specific test mode the vendor specific test mode is no longer supported. www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 35 9.8 jack-detect function jd (jack-detect) is an internal, pulled high input pin used to decide if line_out should be auto muted. if jde (jack detect enable) is set and ALC202 detects the jd is floating or pull high (jds=1), the ALC202 will disable the analog output of line_out even when the mx02 is not muted. the first figure below shows an example of jack detect which can implement this function. if no audio plug is inserted in hp_out jack, jd is detected as low, and line output is norma l. if an audio plug is inserted, the ALC202 disables the line output, (mx7a.0=1), spdif output (mx7a.2=1), mono_out (mx7a.3=1), hp_out (mx7a.4=1). this is useful for some pc applications, such as notebook and home based computers. if a headphone output jack is not implemente d and hp_out kept as floating, once jd e is enabled, line_out will be muted (depending if mx7a.4=0) unless jd is pull low by a 10k ? resistor (see second figure). to conquer this disadvantage, the jack-detect mute line_out function is disabled after power up (default jde is 0). this makes the ALC202 compatible with other ac?97 devices. therefore, it is the responsibility of the so ftware to enable this functi on if headphone jack detection is implemented. example of a jack detect circuit jd is pulled low by a 10k ? resistor jd hp-out-r hp-out-l 4.7k hp-out 5 4 3 2 1 + 3.3u 4.7k 4.7k + +100uf + +100uf hp-out-r hp-out-l jd 10k if hp-out jack is not implemented, jd must be pulled low to prevent jds is set www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 36 the figure below shows another simple way to implement the jack detect function without using the jd pin of the ALC202. it is a good circuit for motherboard makers, as it is only a layout issue and no extra components are needed. once the hp_out jack is plugged in, output signals to line_out will be isolated , and no signals will be output to the line_out jack. the only drawback to this plan is that software will not sense that the hp_out jack is plugged in. it may be not convenient for software to pay attention to this special application. implementing the jack-detect function without using the jd pin 9.9 dc voltage volume control the ALC202 has a 32-step internal volume control that is controlled by the dc voltage applied the ?dc vol? pin (pin-33). the volume control input range is from gnd to avdd. a low speed of counter ramp adc transmits the dc voltage into a 5-bit volume code to attenuate the master volume (real mx02), headphone volume (real mx04) and mono-out volume (real mx06). a higher dc voltage means more attenuation related to output volume. the table below shows the relation between input dc voltage and the 5-bit volume code. input dc voltage volume code note input dc voltage volume code note 95%=< dc 1f dcmute=1 47%< dc <= 50% f 92%< dc <= 95% 1e dcmute=0 44%< dc <= 47% e 89%< dc <= 92% 1d 41%< dc <= 44% d 86%< dc <= 89% 1c 38%< dc <= 41% c 83%< dc <= 86% 1b 35%< dc <= 38% b 80%< dc <= 83% 1a 32%< dc <= 35% a 77%< dc <= 80% 19 29%< dc <= 32% 9 74%< dc <= 77% 18 26%< dc <= 29% 8 71%< dc <= 74% 17 23%< dc <= 26% 7 68%< dc <= 71% 16 20%< dc <= 23% 6 65%< dc <= 68% 15 17%< dc <= 20% 5 62%< dc <= 65% 14 14%< dc <= 17% 4 59%< dc <= 62% 13 11%< dc <= 14% 3 56%< dc <= 59% 12 8%< dc <= 11% 2 53%< dc <= 56% 11 5%< dc <= 8% 1 50%< dc <= 53% 10 dc <= 5% 0 dcmute=0 input dc voltage is ratio of avdd (+5va). ? this 5-bit volume code adds extra attenuation for master volume and headphone volume, the absolute maximum volume is determined by mx02, mx04 and mx06. once the sum of mx value and volume code exceeds 3fh, the real mx value is 3fh. hp-out-r hp-out-l hp-out 1 2 3 4 5 + +100uf + +100uf line-out 1 2 3 4 5 a simple way to implement jack-detect function without using ALC202's jd pin www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 37 example 1: (normal case) mx02=0002h, mx04=0300h, mx06=0001h, volume code=2h, then master volume=0204h, headphone volume=0502h, mono-out=0003h example 2: (the sum exceeds 3fh for mx02/mx04, 1fh for mx06) mx02=2f2fh, mx04=2e2eh, mx06=0002h, volume code=1eh, then master volume=3f3fh, real headphone volume=3d3dh, mono-out=001fh example 3: (volume code is 1fh, dcmute=1, real mxs should be muted) mx02=0000h, mx04=2020h, mx06=0010h, volume code=1fh, then master volume=9f1fh, headphone volume=bf3fh, mono-out=801fh 9.10 power off cd function the ?power off cd? function describes a state which, after the system has been shut down and a +5v analog power is supplied at vaux, the ALC202 will turn on the cd-in op and output am plifier. it is possible to design a system which will save op-amp circuitry and bypass cd output directly to the speaker. the figure below indicates the system application circuitry to support the ?power off cd? function. the operation mode is defined by +3.3vcc and +5vaux. +3.3vcc +5vaux operation mode no (0) no (0) shut down no (0) yes (1) power off cd yes (1) no (0) normal (+5vaudio must be on) yes (1) yes (1) normal (+5vaudio must be on) +5vaux +3.3vcc +5vaudio cd-r cd-gnd cd-l c19 1u u1 ALC202 / ALC202a 1 9 25 38 4 7 26 42 2 3 5 6 8 10 11 12 13 14 15 16 17 18 20 19 21 22 23 24 27 28 29 30 31 32 33 34 35 36 37 39 40 41 43 44 45 46 47 48 vdd vdd avdd avdd gnd gnd agnd agnd xtl-in xtl-out/xtlsel# sdout bitclk sdin sync reset# pc-beep phone aux-l aux-r video-l video-r cd-l cd-r cd-gnd mic1 mic2 line-l line-r vref vrefout afilt1 afilt2 vrad vrda dcvol vaux lineout-l lineout-r mono-out hpout-l nc hpout-r gpio0 gpio1 id0# id1# eapd/jd spdifo c18 1u c20 1u c9 0.1u c25 0.1u + c38 10u + c1 10u d3 1n5817m/cyl d2 1n5817m/cyl r19 0 r20 0 r18 0 j1 ide 1 2 3 4 vaux cd-in power off cd circuitry www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 38 10. application circuit filter connection schematic y1 24.576m x x id=00 x 22pf x r45 x x ext. 14.318m 0 (primary) c3 x c2 r2b 0.01uf r46 r2c x crystal c2a 0 table-1. clock source r2a 22pf x 00x xx xxx x ext. 14.318m 10k 10k 0 r2a,r2b and c2a can bias external clock to acceptible level if external clock is weak. filter connection table +3.3vdd +12v +3.3vdd pcspk phone aux-l aux-r video-l video-r cd-l cd-r mic1 mic2 line-l line-r cdgnd lout-l hp-out-r hp-out-l vrefout spdifo mono-o lout-r ext-14.318m jd dcvol gpio0 gpio1 +5vaux bitclk -reset sync sdout sdin +5va sdin vrefout -reset sync sdout +5va r2c 0 c49 0.1u c19 1u r45 0 1u c37 r2a 10k r2b 10k c2 22p c3 22p y1 24.576mhz c2a 0.01u u1 ALC202 / ALC202a 1 9 25 38 4 7 26 42 2 3 5 6 8 10 11 12 13 14 15 16 17 18 20 19 21 22 23 24 27 28 29 30 31 32 33 34 35 36 37 39 40 41 43 44 45 46 47 48 vdd vdd avdd avdd gnd gnd agnd agnd xtl-in xtl-out/xtlsel# sdout bitclk sdin sync reset# pc-beep phone aux-l aux-r video-l video-r cd-l cd-r cd-gnd mic1 mic2 line-l line-r vref vrefout afilt1 afilt2 vrad vrda dcvol vaux lineout-l lineout-r mono-out hpout-l nc hpout-r gpio0 gpio1 id0# id1# eapd/jd spdifo c22 1u c21 1u c24 1u c23 1u c20 1u c18 1u c17 1u c16 1u c15 1u c13 1u c12 1u c32 1u c14 1u c30 1n c29 1n c31 1u c28 22p + c41 100uf + c39 100uf + c38 10u c25 0.1u c9 0.1u + c1 10u r46 0 + c35 100uf + c27 4.7u / 10u + c36 100uf u2 lm7805ct 1 3 2 in out gnd + c48 +10u + c47 +10u r44 10 select 14.318m clock, refer to t 14.318mhz external clock if 24.576mhz crystal is used ALC202: 60mw@8ohm amp at pin-39/41 reserved the recommended regulator must supply at least output current to prevent from overheating. r46=on, r45=x: use 14.318mhz clo c r46=on, r45=on: use 14.318mhz cl o r46=x, r45=x: use 24.576mhz crys t tied at one point only under the codec or near the codec dgnd agnd ALC202a: 60mw@8ohm amp at pin-35/36 www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 39 io connection +5va cd-l line-r line-l video-l aux-l cdgnd lout-r lout-l mic1 vrefout pcspk pc-speaker cd-r aux-r hp-out-r jd hp-out-l hp-out-r hp-out-l jd dcvol video-r r47 4.7k r41 0 / 20 r39 0 / 20 r41a 4.7k r21 1k r39a 4.7k ph4 hp-out 1 2 3 4 5 j1 ide 1 2 3 4 r24 0 r23 0 ph2 line in ph1 line out r28 4.7k ph3 mic in c21b 4700p r36 0 / 20 r35 0 / 20 r18 0 r20 0 r19 0 ce 100p ce 100p ce 100p ce 100p r39a 4.7k r41a 4.7k r39 0 / 20 r41 0 / 20 + 3.3u ph4 hp-out 5 4 3 2 1 r12a 10k r12b 4.7k c12a 100p r47 4.7k j2 aux-in 1 2 3 4 r33 10k j3 video-in 1 2 3 4 + c47 3.3u d1 1n4008 ce 100p ce 100p cd-in reserved hp-out jack-detection circuit with isolated phonejack hp-out jack-detection circuit with stereo phonejack dc voltage volue control block fine tune performace or adjust input full swing to meet pc99 block-a block-a block-a: *if system designer use +5va regulator has less then 200ma output current capability, please modify r39 and r41 as 20 ohm to limit amplifier current. (ALC202) volume down volume up *if system designer use +5va regulator has less then 200ma output current capability, please modify r35 and r36 as 20 ohm to limit amplifier current. (ALC202a) www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 40 spdifo vdd r101 100 r102 360 u3 sn75179 1 2 3 4 8 7 6 5 vcc r d gnd a b z y t1 pe-65612 t2 rca connector s/pdif output 1 2 c101 0.1u the t1 transformer should be capable of operating from 1.5m to 7mhz (with lower shunt capacitor is preferred) 1 2 3 4 s/pdif signal use rca connector option (i): + line driver/ receiver (is suitable for long transmission line) spdifo spdifo t4 rca connector s/pdif output 1 2 t3 pe-65612 r108 0 r103 0 r106 360 r105 100 option (iii): without line driver/ receiver use r103 and r108: guaranteed transmission distance <= 7 feet 1 2 3 4 use t3,r105,r106: at least 10 feet of transmission distance +5vdd +5vdd spdifo +5vdd spdifo r110 8.2k u4 totx176 4 3 2 1 5 6 in vcc led gnd n.c n.c (bottom view) u5 totx178a 3 2 1 input vcc gnd n.c n.c c102 0.1u s/pdif signal use fiber optic transmitter (optical transmitter) option (ii): totx176 - maximum 10m transmission distance (optical transmitter) totx178 - maximum 5m transmission distance s/pdif output connection (i, ii, iii are optional) www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 41 11. mechanical dimensions millimeter inch symbol min. typical max. min. typical max a 1.60 0.063 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 c 0.09 0.20 0.004 0.008 d 9.00 bsc 0.354 bsc d1 7.00 bsc 0.276 bsc d2 5.50 0.217 e 9.00 bsc 0.354 bsc e1 7.00bsc 0.276 bsc e2 5.50 0.217 b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 bsc 0.016 bsc th 0 o 3.5 o 7 o 0 o 3.5 o 7 o l 0.45 0.60 0.75 0.018 0.0236 0.030 l1 1.00 0.0393 title: lqfp-48 (7.0x7.0x1.6mm) package outline drawing, footprint 2.0mm leadframe material doc. no. approve version 02 dwg no. pkgc-065 check date realtek semiconductor corp. l1 l www.datasheet.co.kr datasheet pdf - http://www..net/
ALC202/ALC202a 2002/07/30 rev.1.28 42 12. revision history version 1.27: (1) 14.318mhz 24.576mhz pll is enabled when pin-46 is pulled low. 48mhz 24.576mhz pll is no longer supported. version 1.28: (1) fix typing error in f ilter connection schematic. realtek/avance logic, inc. headquarters 1f, no. 2, industry east road ix, science-based industrial park, hsinchu, 300, taiwan, r.o.c. tel : 886-3-5780211 fax : 886-3-5776047 www: www.realtek.com.tw www.datasheet.co.kr datasheet pdf - http://www..net/

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